The invention relates to a processing arrangement particularly for decoding a digital signal consisting of binary elements which are produced at a frequency F and result from the coding of an analog signal by means of delta modulation.
It is known that in a transmission system using delta modulation, the transmitter furnishes a sequence of binary elements whose values are obtained from comparisons, effected at sampling instants of frequency F, between the value of the analog signal to be transmitted and the value of the signal furnished by a local decoder, comprising an integrator circuit, to which a signal, derived from the emitter digital signal, is applied.
In the receiver a sequence of binary elements which is identical to that furnished by the transmitter is formed on the basis of the received signals, these binary elements being produced using the same sampling frequency F. The resulting digital signal is used in a decoder, identical to that of the transmitter, for controlling the signal applied to an integrating circuit. This integrating circuit supplies a signal which varies with a positive or a negative step at each sampling period and which is an approximated reconstruction of the initial analog signal. In the simplest systems, the size of this quantisation step is constant. In more elaborate systems, the transmitter and the receiver are provided with corresponding compression and expansion devices which automatically adapt the size of the step to the dynamics of the analog signal so that the sampling frequency F can be reduced. But in all cases the reconstructed signal furnished by the integrating circuit comprises parasitic components of the frequency F which can have a relatively important amplitude and which must be eliminated by means of a low-pass filter.